1. Field of the Invention
The present invention relates to a semiconductor device having buried elements with element with electrical and a manufacturing method thereof, and more particularly to a SOI (Silicon On Insulator) substrate in which electrical elements such as capacitor, resistor, connecting line or the like are previously buried on any wafer and are bonded with other wafer, a manufacturing method the SOI substrate having buried elements.
2. Description of the Prior Art
As shown in FIG. 1A to 1C, a prior art SDB (Silicon Director Bonding) process is disclosed in which a seed wafer and a handling wafer are bonded from each other to form a SOI substrate.
FIG. 1A are cross-sectional views showing the two wafers around which oxide films are deposited respectively.
In FIG. 1A, the oxide films 2 and 4 having about 5000 .ANG. are deposited around the seed wafer 1 and the handling wafer 3, respectively, subsequently, the seed wafer 1 and handling wafer 3 thus deposited is subjected to a well-known bonding process to bond the two wafers. The bonding process is carried out in a typical manner; for example, maintaining the seed wafer 1 in contact with the handling wafer 3 at about 800.degree. C. under supply of voltage pulse (about 100-500 V).
In addition, a substrate 5 in which the two wafers are contacted is subjected to a thermal process in order to raise the adhesive strength of the two wafers. The thermal process is carried out in a typical manner; for example, maintaining the substrate 5 thus contacted at 900.degree.-1100.degree. C. in a nitrogen atmosphere or an oxygen atmosphere for about 30 min (as shown in FIG. 1B). With respect to FIG. 1B, reference number 6 is a contact portion of the oxide films between the two wafers. Through the thermal process, the substrate thus formed is more than 100 Kg/cm.sup.2 in the adhesive strength.
FIG. 1C shows a SOI substrate polished by a well-known polishing process. In FIG. 1C, the seed wafer 1 is polished into planarization by means of a mechanical or chemical polishing process in order to form a SOI substrate 7 in which the seed wafer thus polished is isolated from the handling wafer 3 by the contact portion 6 formed as thick as about 1 .mu.m.
Such a prior art as described above is disclosed in European Patent 274801 to Alexander, et al.
As shown in FIG. 2A to 2D, another prior art P-SDB (poly-crystalline to Silicon Direct Bonding) process is disclosed. In FIG. 2A, firstly, on the seed wafer 17 is formed a mesa pattern 10 having about 1000 .ANG. in thickness, and then after forming an oxide layer 11 of 1 m in thickness on the seed wafer 17 provided with the mesa pattern 10 a polysilicon layer 12 having 5 .mu.m in thickness is deposited on the oxide layer 11. The mesa pattern 10 means a rugged shape in which concave portions are spaced in matrix on the surface of the seed wafer.
FIG. 2B shows a wafer polished by a polishing process. With respect to FIG. 2B, the polysilicon layer 12 on the seed wafer 17 is polished into planarization to remove rugged portions in the surface of the polysilicon layer 12 and to form a mirror surface 13 on the polysilicon layer.
In turn, an oxide layer for connection is formed on the surface of a handling wafer 16, respectively, and then the mirror surface 13 of the polysilicon layer is bonded with the handling wafer 16 through the oxide layer 15 by means of a P-SDB process similar to the above-mentioned SDB process, as shown in FIG. 2C.
FIG. 2D shows a SOI substrate formed by the well-known polishing process for planarization of the seed wafer. FIG. 2D, the polishing process of the seed wafer 16 is carried out in succession until the upper surface of the oxide layer 11 is exposed. Then, the oxide layer 11 serves as a polishing stopper so that thickness of a SOI 14 thus formed may be controlled by depth of the concave portion in the mesa pattern 10 of the seed wafer 17.
As described above, since the polysilicon layer 12 in the prior art P-SDB process is used for preventing occurrence of the rugged portions caused by the mesa pattern 10 of the seed wafer 17, and is polished into planarization of a bonding interface on the seed wafer, and therefore it is easy to bond the seed wafer and the handling wafer.
However, in the prior arts for manufacturing a SOI substrate in which a seed wafer is bonded with a handling wafer before formation of electrical element on a seed wafer, since after bonding the two wafers electrical elements is formed in the seed wafer of the SOI substrate, the SOI substrate thus manufactured is lowered in efficiency of chip area.